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february 1996 nds9952a dual n & p-channel enhancement mode field effect transistor general description features ________________________________________________________________________________ absolute maximum ratings t a = 25c unless otherwise noted symbol parameter n-channel p-channel units v dss drain-source voltage 30 -30 v v gss gate-source voltage 20 20 v i d drain current - continuous (note 1a) 3.7 2.9 a - pulsed 15 10 p d power dissipation for dual operation 2 w power dissipation for single operation (note 1a) 1.6 (note 1b) 1 (note 1c) 0.9 t j ,t stg operating and storage temperature range -55 to 150 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 78 c/w r q jc thermal resistance, junction-to-case (note 1) 40 c/w nds9952a .sam these dual n- and p -channel enhancement mode power field effect transistors are produced using fairchild's proprietary, high cell density, dmos technology. this very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. these devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. n-channel 3.7a, 30v, r ds(on ) =0.08 w @ v gs =10v. p-channel - 2.9 a, -30 v, r ds(on ) = 0.13 w @ v gs =-10v. high density cell design or extremely low r ds(on) . high power and current handling capability in a widely used surface mount package. dual (n & p-channel) mosfet in surface mount package. 1 5 6 7 8 4 3 2 ? 1997 fairchild semiconductor corporation
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions type min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a n-ch 30 v v gs = 0 v, i d = - 250 a p-ch -30 v i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v n-ch 2 a t j = 55c 25 a v ds = -24 v, v gs = 0 v p-ch -2 a t j = 55c -25 a i gssf gate - body leakage, forward v gs = 20 v, v ds = 0 v all 100 na i gssr gate - body leakage, reverse v gs = -20 v, v ds = 0 v all -100 na on characteristics (note 2 ) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a n-ch 1 1.7 2.8 v t j = 125c 0.7 1.2 2.2 v ds = v gs , i d = -250 a p-ch -1 -1.6 -2.8 t j = 125c -0.85 -1.25 -2.5 r ds(on) static drain-source on-resistance v gs = 10 v, i d = 1.0 a n-ch 0.06 0.08 w t j = 125c 0.08 0.13 v gs = 4.5 v, i d = 0.5 a 0.08 0.11 t j = 125c 0.11 0.18 v gs = -10 v, i d = -1.0 a p-ch 0.11 0.13 t j = 125c 0.15 0.21 v gs = -4.5 v, i d = -0.5 a 0.17 0.2 t j = 125c 0.24 0.32 i d (on) on-state drain current v gs = 10 v, v ds = 5 v n-ch 15 a v gs = -10 v, v ds = -5 v p-ch -10 g fs forward transconductance v ds = 15 v, i d = 3.7 a n-ch 6 s v ds = -15 v, i d = -2.9 a p-ch 4 dynamic characteristics c iss input capacitance n-channel v ds = 10 v, v gs = 0 v, f = 1.0 mhz p-channel v ds = -10 v, v gs = 0 v, f = 1.0 mhz n-ch 320 pf p-ch 350 c oss output capacitance n-ch 225 pf p-ch 260 c rss reverse transfer capacitance n-ch 85 pf p-ch 100 nds9952a .sam
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions type min typ max units switching characteristics (note 2 ) t d(on) turn - on delay time n-channel v dd = 10 v, i d = 1 a, v gen = 1 0 v, r gen = 6 w p -channel v dd = -10 v, i d = -1 a, v gen = -10 v, r gen = 6 w n-ch 10 15 ns p-ch 9 40 t r turn - on rise time n-ch 13 20 ns p-ch 21 40 t d(off) turn - off delay time n-ch 21 50 ns p-ch 21 90 t f turn - off fall time n-ch 5 50 ns p-ch 8 50 q g total gate charge n-channel v ds = 10 v, i d = 3.7 a, v gs = 10 v p -channel v ds = -10 v, i d = -2.9 a, v gs = -10 v n-ch 9.5 27 nc p-ch 10 25 q gs gate-source charge n-ch 1.5 nc p-ch 1.6 q gd gate-drain charge n-ch 3.3 nc p-ch 3.4 drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current n-ch 1.2 a p-ch -1.2 v sd drain-source diode forward voltage v gs = 0 v, i s = 1 .25 a (note 2 ) n-ch 0.8 1.3 v v gs = 0 v, i s = -1 .25 a (note 2 ) p-ch -0.8 -1.3 t rr reverse recovery time v gs = 0 v, i f = 1.2 5 a, di f /dt = 100 a/s n-ch 75 ns v gs = 0 v, i f = -1.2 5 a, di f /dt = 100 a/s p-ch 100 notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. p d ( t ) = t j - t a r q j a ( t ) = t j - t a r q j c + r q c a ( t ) = i d 2 ( t ) r d s ( o n ) t j typical r q ja for single device operation using the board layouts shown below on 4.5"x5" fr-4 pcb in a still air environment : a. 78 o c/w when mounted on a 0.5 in 2 pad of 2oz cpper. b. 125 o c/w when mounted on a 0.02 in 2 pad of 2oz cpper. c. 135 o c/w when mounted on a 0.003 in 2 pad of 2oz cpper. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. nds9952a .sam 1a 1b 1c
nds9952a .sam 0 1 2 3 0 5 10 15 20 v , drain-source voltage (v) i , drain-source current (a) 6.0 5.0 4.5 4.0 3.5 v =10v gs ds d 8.0 3.0 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j v = 10v gs i = 3.7a d r , normalized ds(on) -50 -25 0 25 50 75 100 125 150 0.6 0.7 0.8 0.9 1 1.1 1.2 t , junction temperature (c) gate-source threshold voltage j i = 250a d v = v ds gs v , normalized th 0 3 6 9 12 15 0.5 1 1.5 2 2.5 3 i , drain current (a) drain-source on-resistance v = 3.5v gs d r , normalized ds(on) 8.0 6.0 10 4.5 5.0 4.0 0 3 6 9 12 15 0.5 1 1.5 2 i , drain current (a) drain-source on-resistance t = 125c j 25c d v = 10 v gs -55c r , normalized ds(on) typical electrical characteristics: n-channel figure 1. n-channel on-region characteristics. figure 2. n-channel on-resistance variation wit h gate voltage and drain current. figure 3. n-channel on-resistance variation with temperature. figure 4. n-channel on-resistance variation with drain current and temperature. figure 5. n-channel transfer characteristics. figure 6. n-channel gate threshold variation with temperature. 1 2 3 4 5 0 2 4 6 8 10 v , gate to source voltage (v) i , drain current (a) 25c 125c v = 10v ds gs d t = -55c j
nds9952a .sam -50 -25 0 25 50 75 100 125 150 0.92 0.96 1 1.04 1.08 1.12 t , junction temperature (c) drain-source breakdown voltage i = 250a d bv , normalized dss j 0.2 0.4 0.6 0.8 1 1.2 1.4 0.001 0.01 0.1 0.5 1 5 10 v , body diode forward voltage (v) i , reverse drain current (a) t = 125c j 25c -55c v = 0v gs sd s 0 2 4 6 8 10 12 0 2 4 6 8 10 q , gate charge (nc) v , gate-source voltage (v) g gs i = 3.7a d 20v 15v v = 10v ds 0.1 0.2 0.5 1 2 5 10 30 50 100 200 300 500 800 1000 v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0v gs c oss c rss figure 7. n-channel breakdown voltage variation with temperature. figure 8. n-channel body diode forward voltage variation with current and temperature . figure 9. n-channel capacitance characteristics. figure 10. n-channel gate charge characteristics. typical electrical characteristics: n-channel (continued) 0 2 4 6 8 10 0 2 4 6 8 10 i , drain current (a) g , transconductance (siemens) t = -55c j 25c d fs v =10v ds 125c figure 11. n-channel transconductance variation with drain current and temperature.
nds9952a .sam -5 -4 -3 -2 -1 0 -20 -15 -10 -5 0 v , drain-source voltage (v) i , drain-source current (a) v = -10v gs ds d -4.0 -6.0 -5.0 -4.5 -7.0 -3.5 -8.0 -3.0 -5.5 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j v = -10v gs i = -2.9a d r , normalized ds(on) -50 -25 0 25 50 75 100 125 150 0.7 0.8 0.9 1 1.1 1.2 t , junction temperature (c) gate-source threshold voltage i = -250a d v = v ds gs j v , normalized th -15 -12 -9 -6 -3 0 0.5 1 1.5 2 2.5 3 i , drain current (a) drain-source on-resistance d r , normalized ds(on) v = -3.5v gs -10 -6.0 -4.0 -8.0 -7.0 -5.0 -4.5 -5.5 -15 -12 -9 -6 -3 0 0.5 1 1.5 2 i , drain current (a) drain-source on-resistance t = 125c j 25c -55c d v = -10v gs r , normalized ds(on) typical electrical characteristics: p-channel (continued) figure 12 . p-channel on-region characteristics. figure 13 . p-channel on-resistance variation wit h gate voltage and drain current. figure 14 . p-channel on-resistance variation with temperature. figure 15 . p-channel on-resistance variation with drain current and temperature. figure 16 . p-channel transfer characteristics. figure 17 . p-channel gate threshold variation with temperature. -6 -5 -4 -3 -2 -1 -10 -8 -6 -4 -2 0 v , gate to source voltage (v) i , drain current (a) v = -10v ds gs d t = -55c j 25c 125c
nds9952a .sam -50 -25 0 25 50 75 100 125 150 0.94 0.96 0.98 1 1.02 1.04 1.06 1.08 1.1 t , junction temperature (c) drain-source breakdown voltage i = -250a d bv , normalized dss j 0.2 0.4 0.6 0.8 1 1.2 1.4 0.001 0.01 0.1 0.5 1 5 10 -v , body diode forward voltage (v) -i , reverse drain current (a) t = 125c j 25c -55c v = 0v gs sd s 0 2 4 6 8 10 12 0 2 4 6 8 10 q , gate charge (nc) -v , gate-source voltage (v) g gs i = -2.9a d v = -10v ds -20v -15v 0.1 0.2 0.5 1 2 5 10 30 50 100 200 300 500 800 1000 -v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0v gs c oss c rss figure 18 . p-channel breakdown voltage variation with temperature. figure 19 . p-channel body diode forward voltage variation with current and temperature . figure 20 . p-channel capacitance characteristics. figure 21 . p-channel gate charge characteristics. typical electrical characteristics: p-channel (continued) -10 -8 -6 -4 -2 0 0 1 2 3 4 5 6 i , drain current (a) g , transconductance (siemens) t = -55c j 25c 125c v = -15v ds d fs figure 22 . p-channel transconductance variation with drain current and temperature.
nds9952a .sam typical thermal characteristics: n & p-channel 0 0.1 0.2 0.3 0.4 0.5 1 2 3 4 5 2oz copper mounting pad area (in ) i , steady-state drain current (a) 2 1c 1b 1a 4.5"x5" fr-4 board t = 25 c still air v = 10v a o gs d figure 24 . n-ch maximum steady- state drain current versus copper mounting pad area. 0 0.1 0.2 0.3 0.4 0.5 1 2 3 4 5 2oz copper mounting pad area (in ) i , steady-state drain current (a) 2 1c 1b 1a 4.5"x5" fr-4 board t = 25 c still air v = -10v a o gs d figure 25 . p-ch maximum steady- state drain current versus copper mounting pad area. 0.1 0.2 0.5 1 2 5 10 30 50 0.01 0.03 0.1 0.3 1 3 10 30 v , drain-source voltage (v) i , drain current (a) ds d dc 1s 10ms 100ms 10s 1ms rds(on) limit 100us v = 10v single pulse r = see note 1c t = 25c gs a q ja figure 26 . n-channel maximum safe operating area. 0.1 0.2 0.5 1 2 5 10 30 50 0.01 0.03 0.1 0.3 1 3 10 30 - v , drain-source voltage (v) -i , drain current (a) ds d rds(on) limit 1s 100ms 10s dc 10ms 1ms 100us v = -10v single pulse r = see note 1c t = 25c gs a q ja figure 27 . p-channel maximum safe operating area . 0 0.2 0.4 0.6 0.8 1 0.5 1 1.5 2 2.5 2oz copper mounting pad area (in ) steady-state power dissipation (w) 2 1c 1b 4.5"x5" fr-4 board t = 25 c still air a o power for single operation total power for dual operation 1a figure 23 . so-8 dual package maximum steady-state power dissipation versus copper mounting pad area.
nds9952a .sam g d s v dd r l v v in out v gs dut r gen 10% 50% 90% 10% 90% 90% 50% v in v out on off d(off) f r d(on) t t t t t t 10% pulse width figure 29 . n or p-channel switching test circuit . figure 30 . n or p-channel switching waveforms . typical thermal characteristics: n & p-channel 0.0001 0.001 0.01 0.1 1 10 100 300 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 duty cycle, d = t / t 1 2 r (t) = r(t) * r r = see note 1c q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2 figure 28 . transient thermal response curve . note: thermal characterization performed using the conditions described in note 1c. transient thermal response will change depending on the circuit board design.
soic(8lds) packaging configuration: figure 1.0 components leader tape 1680mm minimum or 210 empty pockets trailer tape 640mm minimum or 80 empty pockets soic(8lds) tape leader and trailer configuration: figure 2.0 cover tape carrier tape note/comments packaging option soic (8lds) packaging information standard (no flow code) l86z f011 packaging type reel size tnr 13" dia rail/tube - tnr 13" dia qty per reel/tube/bag 2,500 95 4,000 box dimension (mm) 343x64x343 530x130x83 343x64x343 max qty per box 5,000 30,000 8,000 d84z tnr 7" dia 500 184x187x47 1,000 weight per unit (gm) 0.0774 0.0774 0.0774 0.0774 weight per reel (kg) 0.6060 - 0.9696 0.1182 f63tn label esd label 343mm x 342mm x 64mm standard intermediate box esd label f63tnr label sample f63tnlabel lot: cbvk741b019 fsid: fds9953a d/c1: d9842 qty1: spec rev: spec: qty: 2500 d/c2: qty2: cpn: n/f: f (f63tnr)3 f 852 nds 9959 soic-8 unit orientation f 852 nds 9959 pin 1 static dissipative embossed carrier tape
? 1998 fairchild semiconductor corporation dimensions are in millimeter pkg type a0 b0 w d0 d1 e1 e2 f p1 p0 k0 t wc tc soic (8lds) (12mm) 6.50 +/-0.10 5.30 +/-0.10 12.0 +/-0.3 1.55 +/-0.05 1.60 +/-0.10 1.75 +/-0.10 10.25 min 5.50 +/-0.05 8.0 +/-0.1 4.0 +/-0.1 2.1 +/-0.10 0.450 +/- 0.150 9.2 +/-0.3 0.06 +/-0.02 p1 a0 d1 p0 f w e1 d0 e2 b0 tc wc k0 t dimensions are in inches and millimeters tape size reel option dim a dim b dim c dim d dim n dim w1 dim w2 dim w3 (lsl-usl) 12mm 7" dia 7.00 177.8 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 2.165 55 0.488 +0.078/-0.000 12.4 +2/0 0.724 18.4 0.469 0.606 11.9 15.4 12mm 13" dia 13.00 330 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 7.00 178 0.488 +0.078/-0.000 12.4 +2/0 0.724 18.4 0.469 0.606 11.9 15.4 see detail aa dim a max 13" diameter option 7" diameter option dim a max see detail aa w3 w2 max measured at hub w1 measured at hub dim n dim d min dim c b min detail aa notes: a0, b0, and k0 dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c). 20 deg maximum component rotation 0.5mm maximum 0.5mm maximum sketch c (top view) component lateral movement typical component cavity center line 20 deg maximum typical component center line b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation user direction of feed soic(8lds) embossed carrier tape configuration: figure 3.0 soic(8lds) reel configuration: figure 4.0 so-8 tape and reel data and package dimensions, continued july 1999, rev. b
soic-8 (fs pkg code s1) 1 : 1 scale 1:1 on letter size paper di me n si o n s s h ow n be l ow a re in : inches [millimeters] part weight per unit (gram): 0.0774 so-8 tape and reel data and package dimensions, continued september 1998, rev. a 9
trademarks acex? bottomless? coolfet? crossvolt? e 2 cmos tm fact? fact quiet series? fast fastr? gto? the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. supersot?-8 syncfet? tinylogic? uhc? vcx? hisec? isoplanar? microwire? pop? powertrench qfet? qs? quiet series? supersot?-3 supersot?-6 ? rev. e ?

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